Low-Complexity One-Dimensional Parallel Semi-Systolic Structure for Field Montgomery Multiplication Algorithm Perfect for Small IoT Edge Nodes

The use of IoT technology in several applications is hampered by security and privacy concerns with edge nodes. Security flaws can only be resolved implementing cryptographic protocols on these resource constraints the nodes make it extremely difficult to implement protocols. majority protocols’ fundamental operation finite-field multiplication, their performance significantly impacted effective implementation. Therefore, this work mainly focuses low-area low-energy high-speed one-dimensional bit-parallel semi-systolic multiplier for Montgomery multiplication algorithm. space delay complexity analysis proposed structure reveals that design has a significant reduction marginal area when compared competitive multipliers. obtained ASIC synthesis report demonstrates suggested architecture saves amount as well time, area–delay product (ADP), power–delay (PDP) ones. results indicate layout very appropriate devices limited resources such tiny embedded devices.